Trends4Tomorrow (March 6, 2009) — The worlds first integrated circuit using “three-dimensional synchronization circuitry” is now running at 1.4 gigahertz at the University of Rochester.  Unlike past attempts at 3-D chips, the Rochester chip is not simply a number of regular processors stacked on top of one another. It was designed and built specifically to optimize all key processing functions vertically, through multiple layers of processors, the same way ordinary chips optimize functions horizontally. The design means tasks such as synchronization, power distribution, and long-distance signaling are all fully functioning in three dimensions for the first time.

The Rochester team refers to circuitry as a “cube” rather than a “chip.”  And insist that,  “This is the way computing is going to have to be done in the future. They can do things you could never do with a regular 2D chip."

Many experts in the integrated circuit industry are talking about the limits of miniaturization, a point at which it will be impossible to pack more transistors onto the surface of a chip. When this limit is reached, the capabilities of future processors' will be seriously constrained.

To meet this challenge, a number of integrated circuit designers already anticipate expanding into the third dimension: stacking transistors on top of each other.  But, this vertical expansion will create a host of difficulties. 

The key is to overcoming them is to design a 3-D chip where all the layers interact as a single system. But, getting all three dimensions of a 3-D microprocessor chip to act in harmony is like:

• trying to devise a traffic control system for the entire United States,
• then layering two more countries like the United States above the first, and
• getting every bit of traffic from any point on any level to its destination on any other level,
• while simultaneously coordinating the traffic of millions of other drivers. 

The realities of complex systems is actually more like exchanging the two of the United States layers for China and India, where the driving laws and roads are quite different,

In short, the complexity and challenge of designing such a single control system standard to work for any kind of chip begins to become apparent.

Since each layer could be a different processor with a different function, the 3-D chip is essentially an entire circuit board folded up into a tiny package.  The results could mean that an iPod could be compacted to a tenth of its current size with ten times the speed, without changing the size of the transistors.

What makes it all possible is the architecture the Rochester team has designed.  It uses many of the tricks of regular processors, but also accounts for:

• different impedances that might occur from chip-to-chip,
• different operating speeds, and
• different power requirements.

The fabrication of the chip is unique as well. Manufactured at MIT, the chip must have millions of holes drilled into the insulation that separates the layers in order to allow for the myriad vertical connections between transistors in different layers.

Obviously, we’re going to hit a point where we can't scale integrated circuits any smaller horizontally.  But, fortunately we're going to start scaling vertically.  And, that’s probably going to enable Moore’s Law to continue on its current trajectory for another 25 years or more.

Based on materials provided by University of Rochester.